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Programmable Frequency Sweep and Output Burst Waveform Generator AD5930
FEATURES
Programmable frequency profile No external components necessary Output frequency up to 25 MHz Burst and listen capability Preprogrammable frequency profile minimizes number of DSP/controller writes Sinusoidal/triangular/square wave outputs Automatic or single pin control of frequency stepping Waveform starts at known phase Increments at 0 phase or phase continuously Power-down mode: 20 A Power supply: 2.3 V to 5.5 V Automotive temperature range: -40C to +125C 20-lead pb-free TSSOP
GENERAL DESCRIPTION
The AD59301 is a waveform generator with programmable frequency sweep and output burst capability. Utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency-stepped waveforms. Because frequency profiles are preprogrammed, continuous write cycles are eliminated and thereby free up valuable DSP/controller resources. Waveforms start from a known phase and are incremented phase continuously, which allows phase shifts to be easily determined. Consuming only 8 mA, the AD5930 provides a convenient low power solution to waveform generation. The AD5930 can be operated in a variety of modes. In continuous output mode, the device outputs the required frequency for a defined length of time and then steps to the next frequency. The length of time the device outputs a particular frequency is either preprogrammed and the device increments the frequency automatically, or, alternatively, is incremented externally via the CTRL pin. In burst mode, the device outputs its frequency for a length of time and then returns to midscale for a further predefined length of time before stepping to the next frequency. When the MSBOUT pin is enabled, a digital output is generated. (continued on Page 3)
APPLICATIONS
Frequency sweeping/radar Network/impedance measurements Incremental frequency stimulus Sensory applications Proximity and motion BFSK Frequency bursting/pulse trains
FUNCTIONAL BLOCK DIAGRAM
INTERRUPT STANDBY DVDD CAP/2.5V DGND AGND AVDD
AD5930
MCLK
REGULATOR VCC 2.5V SYNC BUFFER SYNCOUT DGND O/P SYNC BUFFER 24-BIT PIPELINED DDS CORE 10-BIT DAC MSBOUT IOUTB IOUT
OUTPUT BURST CONTROLLER DATA CTRL
INCREMENT CONTROLLER INCR DATA FREQUENCY CONTROLLER DATA 24
AND CONTROL CONTROL REGISTER ON-BOARD REFERENCE FULL-SCALE CONTROL COMP
05333-001
SERIAL INTERFACE
FSYNC SCLK
SDATA
REF
FSADJUST
Figure 1.
1
Protected by US Patent Number 6747583, other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD5930 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 6 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 15 Theory of Operation ...................................................................... 16 The Frequency Profile................................................................ 16 Output Modes ............................................................................. 16 Serial Interface ............................................................................ 17 Powering up the AD5930 .......................................................... 17 Programming the AD5930........................................................ 17 Setting up the Frequency Sweep............................................... 19 Activating and Controlling the Sweep..................................... 20 Outputs from the AD5930 ........................................................ 21 Applications..................................................................................... 22 Grounding and Layout .............................................................. 22 AD5930 to ADSP-21xx Interface ............................................. 22 AD5930 to 68HC11/68L11 Interface....................................... 23 AD5930 to 80C51/80L51 Interface .......................................... 23 AD5930 to DSP56002 Interface ............................................... 23 Evaluation Board ........................................................................ 24 Schematic..................................................................................... 25 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27
REVISION HISTORY
11/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5930 GENERAL DESCRIPTION
(continued from Page 1) To program the device, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. The frequency sweep profile is initiated, started, and executed by toggling the CTRL pin. A number of different sweep profiles are offered. Frequencies can be stepped in triangular-sweep mode, which continuously sweeps up and down through the frequency range. Alternatively, in sawsweep mode, the frequency is swept up through the frequency range, but returns to the initial frequency before executing the sweep again. In addition, a single frequency or burst can be generated without any sweep. The AD5930 is written to via a 3-wire serial interface, which operates at clock rates up to 40 MHz. The device operates with a power supply from 2.3 V to 5.5 V. Note that AVDD and DVDD are independent of each other and can be operated from different voltages. The AD5930 also has a standby function, which allows sections of the device that are not being used to be powered down. The AD5930 is available in a 20-lead pb-free TSSOP package.
Rev. 0 | Page 3 of 28
AD5930 SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 k, RLOAD = 200 for IOUT and IOUTB, unless otherwise noted. Table 1.
Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate IOUT Full-Scale2 VOUT Peak-to-Peak VOUT Offset VMIDSCALE Output Compliance DC Accuracy Integral Nonlinearity (INL) Differential Nonlinearity (DNL) DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wideband (0 to Nyquist) Narrowband (200 kHz) Clock Feedthrough Wake-Up Time OUTPUT BUFFER VOUT Peak-to-Peak Output Rise/Fall Time2 VOLTAGE REFERENCE Internal Reference External Reference Range REFOUT Input Impedance Reference TC2 LOGIC INPUTS Input Current VINH, Input High Voltage Min Y Grade1 Typ 10 3 0.56 45 0.325 50 4.0 Max Unit Bits MSPS mA V mV V V LSB LSB Test Conditions/Comments
0.8 1.5 0.75
From 0 V to the trough of the waveform Voltage at midscale output AVDD = 2.3 V, internal reference used3
53
60 -60
-53
dB dBc
fMCLK = 50 MHz, fOUT = fMCLK/4096 fMCLK = 50 MHz, fOUT = fMCLK/4096
-62 -76 -50 1.7 0 12 1.15 1.18 1 25 90 0.1 1.7 2.0 2.8
-52 -73
dBc dBc dBc ms V ns V V k k ppm/C A V V V V V V pF V V pF
fMCLK = 50 MHz, fOUT = fMCLK/50 fMCLK = 50 MHz, fOUT = fMCLK/50 Up to 16 MHz out From standby Typically, square wave on MSBOUT and SYNCOUT
DVDD
1.26 1.3
VIN @ REF pin < Internal VREF VIN @ REF pin > Internal VREF
1
VINL, Input Low Voltage
0.6 0.7 0.8 3 DVDD - 0.4 V 0.4 5
DVDD = 2.3 V to 2.7 V DVDD = 2.7 V to 3.6 V DVDD = 4.5 V to 5.5 V DVDD = 2.3 V to 2.7 V DVDD = 2.7 V to 3.6 V DVDD = 4.5 V to 5.5 V
CIN, Input Capacitance2 LOGIC OUTPUTS2 VOH, Output High Voltage VOL, Output Low Voltage Floating-State O/P Capacitance
ISINK = 1 mA ISINK = 1 mA
Rev. 0 | Page 4 of 28
AD5930
Parameter POWER REQUIREMENTS AVDD/DVDD IAA IDD IAA + IDD Low Power Sleep Mode Min 2.3 3.8 2.4 6.2 20 140
1 2
Y Grade1 Typ
Max 5.5 4 2.7 6.7 85 240
Unit V mA mA mA A A
Test Conditions/Comments fMCLK = 50 MHz, fOUT = fMCLK/7
Device is reset before putting into standby All outputs powered down, MCLK = 0 V, serial interface active All outputs powered down, MCLK active, serial interface active
Operating temperature range is as follows: Y Version: -40C to +125C; typical specifications are at 25C. Guaranteed by design. 3 Minimum RSET = 3.9 k.
100nF
10nF
RSET 6.8V
CAP/2.5V REGULATOR
REFOUT
FSADJUST FULL-SCALE COMP CONTROL
AVDD 10nF
ON-BOARD REFERENCE
AD5930
12
20pF
Figure 2. Test Circuit Used to Test the Specifications
Rev. 0 | Page 5 of 28
05333-002
SIN ROM
10-BIT DAC
IOUT RLOAD 200V
AD5930 TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 2.1
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17
1
Limit at TMIN, TMAX 20 8 8 25 10 10 5 10 5 3 2 x t1 0 10 x t1 8 x t1 2 x t1 2 x t1 2 x t1 20
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns typ ns typ ns typ ns max
Conditions/Comments MCLK period MCLK high duration MCLK low duration SCLK period SCLK high time SCLK low time FSYNC to SCLK falling edge setup time FSYNC to SCLK hold time Data setup time Data hold time Minimum CTRL pulse width CTRL rising edge to MCLK falling edge setup time CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization) CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization) Frequency change to SYNC output, saw sweep, each frequency increment Frequency change to SYNC output, saw sweep, end of sweep Frequency change to SYNC output, triangle sweep, end of sweep MCLK falling edge after 16th clock edge to MSB out
Guaranteed by design, not production tested.
t1
MCLK
t2 t3
Figure 3. Master Clock
t5
SCLK
t4 t8
t7
FSYNC
t6
SDATA
D15
D14
D2
D1
D0
D15
D14
Figure 4. Serial Timing
Rev. 0 | Page 6 of 28
05333-004
t9
t10
05333-003
AD5930
t12
MCLK
CTRL
t11
05333-005
IOUT/IOUTB
t13
Figure 5. CTRL Timing
CTRL
t13
IOUT SYNC O/P (Each Frequency Increment) SYNC O/P (End of Sweep)
t14
05333-006
t15
Figure 6. CTRL Timing, Saw-Sweep Mode
CTRL
t13
IOUT SYNC O/P (Each Frequency Increment) SYNC O/P (End of Sweep)
t14
05333-007
t16
Figure 7. CTRL Timing, Triangular-Sweep Mode
Rev. 0 | Page 7 of 28
AD5930 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter AVDD to AGND DVDD to DGND AGND to DGND CAP/2.5V to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Automotive (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP Package (4-Layer Board) JA Thermal Impedance JC Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating -0.3 V to +6.0 V -0.3 V to +6.0 V -0.3 V to +0.3 V -0.3 V to 2.75 V -0.3 V to DVDD + 0.3 V -0.3 V to AVDD + 0.3 V -40C to +125C -65C to +150C +150C 112C/W 27.6C/W 300C 260(+0/-5)C 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 8 of 28
AD5930 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FSADJUST
1 20 19
IOUTB IOUT AGND STANDBY FSYNC SCLK SDATA CTRL
05333-008
REF 2 COMP 3 AVDD 4 DVDD CAP/2.5V
5 6
AD5930
TOP VIEW (Not to Scale)
18 17 16 15 14 13 12 11
DGND 7 MCLK 8 SYNCOUT
9
INTERRUPT DGND O/P
MSBOUT 10
Figure 8. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 Mnemonic FSADJUST Description Full-Scale Adjust Control. A resistor (RSET) must be connected externally between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is: IOUTFULL-SCALE = 18 x VREFOUT/RSET where VREFOUT = 1.20 V nominal and RSET = 6.8 k typical. Voltage Reference. This pin can be an input or an output. The AD5930 has an internal 1.18 V reference, which is made available at this pin. Alternatively, this reference can be overdriven by an external reference, with a voltage range as given in the Specifications section. A 10 nF decoupling capacitor should be connected between REF and AGND. DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD. Positive Power Supply for the Analog Section. AVDD can have a value from +2.3 V to +5.5 V. A 0.1 F decoupling capacitor should be connected between AVDD and AGND. Positive Power Supply for the Digital Section. DVDD can have a value from +2.3 V to +5.5 V. A 0.1 F decoupling capacitor should be connected between DVDD and DGND. Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD. Ground for all Digital Circuitry. This excludes digital output buffers. Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. Digital Output for Sweep Status Information. User selectable for end of sweep (EOS) or frequency increments through the control register (SYNCOP bit). This pin must be enabled by setting Control Register Bit SYNCOPEN to 1. Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by setting bit MSBOUTEN in the control register to 1. Separate DGND Connection for Digital Output Buffers. Connect to DGND. Digital Input. This pins acts as an interrupt during a frequency sweep. A low to high transition is sampled by the internal MCLK, which resets internal state machines. This results in the DAC output going to midscale. Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition, sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the preprogrammed frequency sweep sequence. When in auto-increment mode, a single pulse executes the entire sweep sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions. Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first followed by the MSB to LSB of the data. Serial Clock Input. Data is clocked into the AD5930 on each falling SCLK edge. Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator are powered down. For optimum power saving, it is recommended to reset the AD5930 before putting it into standby, as this results in a shutdown current of typically 20 A.
2
REF
3 4 5 6
COMP AVDD DVDD CAP/2.5V
7 8 9 10 11 12 13
DGND MCLK SYNCOUT MSBOUT DGND O/P INTERRUPT CTRL
14 15 16 17
SDATA SCLK FSYNC STANDBY
Rev. 0 | Page 9 of 28
AD5930
Pin No. 18 19 Mnemonic AGND IOUT Description Ground for all Analog Circuitry. Current Output. This is a high impedance current source output. A load resistor of nominally 200 should be connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to act as a low-pass filter and to reduce clock feedthrough. In conjunction with IOUTB, a differential signal is available. Current Output. IOUTB is the compliment of IOUT. This pin should preferably be tied through an external load resistor of 200 to AGND, but can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended as a low-pass filter to reduce clock feedthrough. In conjunction with IOUT, a differential signal is available.
20
IOUTB
Rev. 0 | Page 10 of 28
AD5930 TYPICAL PERFORMANCE CHARACTERISTICS
9 8 7 6
SFDR (dBc) IDD (mA)
-40
TA = 25C AVDD = 5V MSBOUT, SYNCOUT ENABLED DVDD = 5V
-45 -50 -55 -60 -65 -70 -75 -80 -85 -90 0
AVDD = DVDD = 3V/5V MCLK = 50MHz CREG = 0111 1111 1111 TA = 25C
FOUT = MCLK/7
5 4 3 2 1 0 0 5 10 15 20
DVDD = 3V
FOUT = MCLK/50
DVDD = 5V, FOUT = MCLK/7
FOUT = MCLK/3
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
Figure 9. Current Consumption (IDD) vs. MCLK Frequency
7 6 5
IDD (mA)
Figure 12. Wideband SFDR vs. MCLK Frequency
TA = 25C MCLK = 50MHz
-60 MSBOUT ON, SYNCOUT ON AVDD = DVDD = 3V/5V MCLK = 50MHz CREG = 0111 1111 1111 TA = 25C FOUT = MCLK/50
-65
4 3 2 1 0
SFDR (dBc)
MSBOUT OFF, SYNCOUT ON
MSBOUT ON, SYNCOUT OFF
-70
-75
FOUT = MCLK/3
MSBOUT OFF, SYNCOUT OFF
-80
05333-028
-85
1kHz 100kHz 1MHz 5MHz 15MHz 25MHz 500kHz 10kHz 500kHz 2MHz 10MHz 20MHz FOUT (Hz)
-90
0
5
10
15
20
25
30
35
40
45
50
MCLK FREQUENCY (MHz)
Figure 10. IDD vs. FOUT for Various Digital Output Conditions
Figure 13. Narrowband SFDR vs. MCLK Frequency
-30
3.5 3.0 2.5 AIDD
-40
AVDD = DVDD = 3V/5V CREG = 0111 1111 1111 TA = 25C
MCLK = 50MHz
-50
IDD (mA)
2.0 1.5 1.0 0.5 0
SFDR (dBc)
DIDD
-60 MCLK = 10MHz -70 MCLK = 1MHz -80
05333-029
1
2
3
4
-90 0.001
0.01
0.1 FOUT (MHz)
1
10
100
CONTROL OPTION (See Legend)
Figure 11. IDD vs. Output Waveform Type and Control
Figure 14. Wideband SFDR vs. FOUT for Various MCLK Frequencies
Rev. 0 | Page 11 of 28
05333-032
LEGEND 1. SINEWAVE OUTPUT, INTERNALLY CONTROLLED SWEEP 2. TRIANGULAR OUTPUT, INTERNALLY CONTROLLED SWEEP 3. SINEWAVE OUTPUT, EXTERNALLY CONTROLLED SWEEP 4. TRIANGULAR OUTPUT, EXTERNALLY CONTROLLED SWEEP
MCLK = 30MHz
05333-031
FOUT = MCLK/7
05333-030
05333-027
DVDD = 3V, FOUT = MCLK/7
AD5930
70 TA = 25C AVDD = DVDD = 5V fOUT = FMCLK/4096
NUMBER OF DEVICES
12
65
10
60
SNR (dB)
8
55
6
50
4
45
05333-034
2
05333-025
40
0
10M
20M
30M
40M
50M
0 552
554
556
558
560
562
564
566
568
570
572
MCLK FREQUENCY (MHz)
VOUT PEAK-TO-PEAK (mV)
Figure 15. SNR vs. MCLK Frequency
1.25 AVDD = DVDD = 5V 1.23
NUMBER OF DEVICES
Figure 18. Histogram of VOUT Peak-to-Peak
12
10
8
VREF (V)
1.21
6
1.19
4
1.17
05333-035
2
05333-026
1.15 -40
-20
0
20
40
60
80
100
120
0 44.4
44.6
44.8
45.0
45.2
45.4
45.6
45.8
46.0
46.2
TEMPERATURE (C)
VOUT OFFSET (mV)
Figure 16. VREF vs. Temperature
2.0 1.9 1.8
WAKE-UP TIME (ms)
Figure 19. Histogram of VOUT Offset
0
AVDD = DVDD = 2.3V
-10 -20
ATTENUATION (dB)
TA = 25C 100mV p-p RIPPLE NO DECOUPLING ON SUPPLIES AVDD = DVDD = 5V
1.7 1.6 1.5 1.4
AVDD = DVDD = 5V
-30
DVDD (on CAP/2.5V)
-40 -50 -60
05333-036
1.2 -40
-20
0
20
40
60
80
100
120
-80 10
100
1k
10k
100k
1M
TEMPERATURE (C)
MODULATING FREQUENCY (Hz)
Figure 17. Wake-up Time vs. Temperature
Figure 20. PSSR
Rev. 0 | Page 12 of 28
05333-033
1.3
-70
AVDD (on IOUT)
AD5930
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 100
0 -10 -20 -30 -40
PHASE NOISE
(dB)
-50 -60 -70 -80
05333-037
-90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz) 5M ST 50 SEC
1k
10k
100k
f (Hz)
Figure 21. Output Phase Noise
Figure 24. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 5555555
0 -10 -20 -30 -40 0 -10 -20 -30 -40
(dB)
(dB)
-50 -60 -70 -80 -90 -100 0 RWB 100 VWB 30 FREQUENCY (Hz)
05333-014
-50 -60 -70 -80 -90 -100 0 RWB 100 VWB 30 FREQUENCY (Hz)
05333-017
100k ST 100 SEC
160k ST 200 SEC
Figure 22. fMCLK = 10 MHz; fOUT = 2.4 kHz, Frequency Word = 000FBA9
0 -10 -20 -30 -40 0 -10 -20 -30 -40
Figure 25. fMCLK = 50 MHz; fOUT = 12 kHz, Frequency Word = 000FBA9
(dB)
(dB)
-50 -60 -70 -80 -90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz) 5M ST 50 SEC
05333-015
-50 -60 -70 -80 -90 -100 0 RWB 100 VWB 300 FREQUENCY (Hz)
05333-018
1.6M ST 200 SEC
Figure 23. fMCLK = 10 MHz; fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492
Figure 26. fMCLK = 50 MHz; fOUT = 120 kHz, Frequency Word = 009D496
Rev. 0 | Page 13 of 28
05333-016
AD5930
0 -10 -20 -30 -40 0 -10 -20 -30 -40
(dB)
-50 -60 -70 -80
05333-019
(dB)
-50 -60 -70 -80 -90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz)
05333-021
-90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz)
25M ST 200 SEC
25M ST 200 SEC
Figure 27. fMCLK = 50 MHz; fOUT = 1.2 MHz, Frequency Word = 0624DD3
0 -10 -20 -30 -40
Figure 29. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7, Frequency Word = 2492492
0 -10 -20 -30 -40
(dB)
(dB)
-50 -60 -70 -80
05333-020
-50 -60 -70 -80 -90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz)
05333-022
-90 -100 0 RWB 1K VWB 300 FREQUENCY (Hz)
25M ST 200 SEC
25M ST 200 SEC
Figure 28. fMCLK = 50 MHz; fOUT = 4.8 MHz, Frequency Word = 189374C
Figure 30. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3, Frequency Word = 5555555
Rev. 0 | Page 14 of 28
AD5930 TERMINOLOGY
Integral Nonlinearity (INL) This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale and full scale. The error is expressed in LSBs. Differential Nonlinearity (DNL) This is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Output Compliance The output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD5930 may not meet the specifications listed in the data sheet. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic that is present in the band of interest. The wide band SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 200 kHz about the fundamental frequency. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD5930, THD is defined as
THD(dB) = 20 log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 V1
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonic. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD5930's output spectrum.
Rev. 0 | Page 15 of 28
AD5930 THEORY OF OPERATION
The AD5930 is a general-purpose synthesized waveform generator capable of providing digitally programmable waveform sequences in both the frequency and time domain. The device contains embedded digital processing to provide a repetitive sweep of a user programmable frequency profile allowing enhanced frequency control. Because the device is preprogrammable, it eliminates continuous write cycles from a DSP/controller in generating a particular waveform.
Triangular-Sweep Mode
In the case of a triangular sweep, the AD5930 repeatedly sweeps between sweep start to sweep end, that is, from FSTART incrementally to FSTART + NINCR x f and then returns to FSTART in a decremented manner (see Figure 32). The triangular-sweep cycle time is given by (1 + (2 x NINCR)) x tINT
THE FREQUENCY PROFILE
The frequency profile is defined by the start frequency (FSTART), the frequency increment (f) and the number of increments per sweep (NINCR). The increment interval between frequency increments, tINT, is either user programmable with the interval automatically determined by the device (auto-increment mode), or externally controlled via a hardware pin (external increment mode). For automatic update, the interval profile can either be for a fixed number of clock periods or for a fixed number of output waveform cycles. In the auto-increment mode, a single pulse at the CTRL pin starts and executes the frequency sweep. In the external increment mode, the CTRL pin also starts the sweep, but the frequency increment interval is determined by the time interval between sequential 0/1 transitions on the CTRL pin. Furthermore, the CTRL pin can be used to directly control the burst profile, where during the input high time, the output waveform is present, and during the input low time, the output is reset to midscale. The frequency profile can be swept in two different modes: saw sweep or triangular (up/down) sweep.
FSTART MIDSCALE FSTART FSTART + NINCR x F FSTART + F FSTART + F FSTART
05333-010
Figure 32. Triangular-Sweep Profile
OUTPUT MODES
The AD5930 offers two possible output modes: continuous output mode and burst output mode. Both of these modes are illustrated in Figure 33.
tINT
CONTINUOUS MODE TBURST BURST MODE
1
2
In the case of a saw sweep, the AD5930 repeatedly sweeps between sweep start to sweep end, that is, from FSTART incrementally to FSTART + NINCR x f and then returns directly to FSTART to begin again (see Figure 31). This gives a saw-sweep cycle time of (NINCR + 1) x tINT
NUMBER STEP CHANGES
Figure 33. Continuous Mode and Burst Mode of the AD5930
Continuous Output Mode
In this mode, each frequency of the sweep is available for the length of time programmed into the time interval (tINT) register. This means the frequency swept output signal is continuously available, and is therefore phase continuous at all frequency increments. To set up the AD5930 in continuous mode, the CW/BURST bit (D7) in the control register must be set to 0. See the Activating and Controlling the Sweep section for more details.
Burst Output Mode
FSTART MIDSCALE
05333-009
FSTART
FSTART + F
FSTART + NINCR x F
In this mode, the AD5930 provides a programmable burst of the waveform output for a fixed length of time (TBURST) within the programmed increment interval (tINT). Then for the remainder of the tINT interval, the output is reset to midscale and remains there until the next frequency increment.
Figure 31. Saw-Sweep Profile
Rev. 0 | Page 16 of 28
05333-011
Saw-Sweep Mode
AD5930
This is beneficial for applications where the user needs to burst a frequency for a set period, and then "listen" for a response before increasing to the next frequency. Note also that the beginning of each frequency increment is at midscale (Phase 0 Rad). Therefore, the phase of the signal is always known. To set up the AD5930 in burst mode, the CW/BURST bit (D7) in the control register must be set to 1. See the Activating and Controlling the Sweep section for more details about the burst output mode.
PROGRAMMING THE AD5930
The AD5930 is designed to provide automatic frequency sweeps when the CTRL pin is triggered. The automatic sweep is controlled by a set of registers, the addresses of which are given in Table 5. The function of each register is described in more detail in the following section. Table 5. Register Addresses
Register Address D15 D14 D13 D12 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 Mnemonic CREG NINCR f f tINT TBURST FSTART FSTART Name Control bits Number of increments Lower 12 bits of delta frequency Higher 12 bits of delta frequency Increment interval Burst interval Lower 12 bits of start frequency Higher 12 bits of start frequency Reserved Reserved
SERIAL INTERFACE
The AD5930 has a standard 3-wire serial interface, which is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP interface standards. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is given in Figure 4. The FSYNC input is a level-triggered input that acts as a frame synchronization and chip enable. Data can only be transferred into the device when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC to SCLK falling edge setup time, t7. After FSYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. FSYNC can be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses, and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low. FSYNC should only go high after the 16th SCLK falling edge of the last word is loaded. The SCLK can be continuous, or, alternatively, the SCLK can idle high or low between write operations.
0 0 1 1
0 1 0 1
The Control Register
The AD5930 contains a 12-bit control register (see Table 6) that sets up the operating modes of the AD5930. The different functions and the various output options from the AD5930 are controlled by this register. Table 7 describes the individual bits of the control register. To address the control register, D15 to D12 of the 16-bit serial word must be set to 0. Table 6. Control Register
D15 0 D14 0 D13 0 D12 0 D11 to D0 Control Bits
POWERING UP THE AD5930
When the AD5930 is powered up, the part is in an undefined state, and therefore, must be reset before use. The eight registers (control and frequency) contain invalid data and need to be set to a known value by the user. The control register should be the first register to be programmed, as this sets up the part. Note that a write to the control register automatically resets the internal state machines and provides an analog output of midscale as it provides the same function as the INTERRUPT pin. Typically, this is followed by a serial loading of all the required sweep parameters. The DAC output remains at midscale until a sweep is started using the CTRL pin.
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AD5930
Table 7. Description of Bits in the Control Register
Bit D15 to D12 D11 Name ADDR Function Register address bits.
B24
D10
DAC ENABLE
D9
SINE/TRI
D8 D7
MSBOUTEN CW/BURST
D6
INT/EXT BURST
D5 D4
INT/EXT INCR MODE
D3
SYNCSEL
D2 D1 D0
SYNCOUTEN Reserved Reserved
Two write operations are required to load a complete word into the FSTART register and the f register. When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first write contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5 for the appropriate addresses. The write to the destination register occurs after both words have been loaded, so the register never holds an intermediate value. When B24 = 0, the 24-bit FSTART /f register operates as two 12-bit registers, one containing the 12 MSBs and the other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered independent of the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. To alter the 12 MSBs or the 12 LSBs, a single write is made to the appropriate register address. Refer to Table 5 for the appropriate addresses. When DAC ENABLE = 1, the DAC is enabled. When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when only using the MSB of the DAC input data (available at the MSBOUT pin). The function of this bit is to control what is available at the IOUT/IOUTB pins. When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information resulting in a sinusoidal signal at the output. When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC. When MSBOUTEN = 1, the MSBOUT pin is enabled. When MSBOUTEN = 0, the MSBOUT is disabled (tri-state). When CW/BURST = 1, the AD5930 outputs each frequency continuously for the length of time or number of output waveform cycles specified in the appropriate register, TBURST. When CW/BURST = 0, the AD5930 bursts each frequency for the length of time/number of cycles specified in the burst register, TBURST. For the remainder of the time within each increment window (TBURST - tINT), the AD5930 outputs a DC value of midscale. In external increment mode, it is defined by the pulse widths on the CTRL pin. This bit is active when D7 = 0 and is also used in conjunction with D5. When the user is incrementing the frequency externally (D5 = 1), D6 dictates whether the user is controlling the burst internally or externally. When INT/EXT BURST = 1, the output burst is controlled externally through the CTRL pin. This is useful if the user is using an external source to both trigger the frequency increments and determine the burst interval. When INT/EXT BURST = 0, the output burst is controlled internally. The burst is pre-programmed by the user into the TBURST register (the burst interval can either be clock-based or for a specified number of output cycles). When D5 = 0, this bit is ignored. When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin. When INT/EXT INCR = 0, the frequency increments are triggered automatically. The function of this bit is to control what type of frequency sweep is carried out. When MODE = 1, the frequency profile is a saw sweep. When MODE = 0, the frequency profile is a triangular (up-down) sweep. This bit is active when D2 = 1. It is user-selectable to pulse at the end of sweep (EOS) or at each frequency increment. When SYNCSEL = 1, the SYNCOP pin outputs a high level at the end of the sweep and returns to zero at the start of the subsequent sweep. When SYNCSEL= 0, the SYNCOP outputs a pulse of 4 x TCLOCK only at each frequency increment. When SYNCOUTEN= 1, the SYNC output is available at the SYNCOP pin. When SYNCOUTEN= 0, the SYNCOP pin is disabled (tri-state). This bit must always be set to 1. This bit must always be set to 1.
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AD5930
SETTING UP THE FREQUENCY SWEEP
As stated previously in The Frequency Profile section, the AD5930 requires certain registers to be programmed to enable a frequency sweep. The following sections discuss these registers in more detail.
Number of Increments (NINCR)
An end frequency, or a maximum/minimum frequency before the sweep changes direction is not required on the AD5930. Instead, this end frequency is calculated by multiplying the frequency increment value (f) by the number of frequency steps (NINCR), and adding it to/subtracting it from the start frequency (FSTART), that is, FSTART + NINCR x f. The NINCR register is a 12-bit register, with the address shown in Table 10. Table 10. NINCR Register Bits
D15 0 D14 0 D13 0 D12 1 D11 to D0 12 bits of NINCR <11...0>
Start Frequency (FSTART)
To start a frequency sweep, the user needs to tell the AD5930 what frequency to start sweeping from. This frequency is stored in a 24-bit register called FSTART. If the user wishes to alter the entire contents of the FSTART register, two consecutive writes must be preformed, one to the LSBs and the other to the MSBs. Note that for an entire write to this register, the Control Bit B24 (D11) should be set to 1 with the LSBs programmed first. In some applications, the user does not need to alter all 24 bits of the FSTART register. By setting the Control Bit B24 (D11) to 0, the 24-bit register operates as two 12-bit registers, one containing the 12 MSBs and the other containing the 12 LSBs. This means that the 12 MSBs of the FSTART word can be altered independently of the 12 LSBs, and vice versa. The addresses of both the LSBs and the MSBs of this register is given in Table 8. Table 8. FSTART Register Bits
D15 1 1 D14 1 1 D13 0 0 D12 0 1 D11 to D0 12 LSBs of FSTART <11...0> 12 MSBs of FSTART <23...12>
The number of increments is programmed in binary fashion, with 000000000010 representing the minimum number of frequency increments (2 increments), and 111111111111 representing the maximum number of increments (4095). Table 11. NINCR Data Bits
D11 0000 0000 D0 0010 Number of Increments 2 frequency increments. This is the minimum number of frequency increments. 3 frequency increments. 4 frequency increments. ... 4094 frequency increments. 4095 frequency increments.
0000 0000 ... 1111 1111
0000 0000 ... 1111 1111
0011 0100 ... 1110 1111
Frequency Increments (f)
The value in the f register sets the increment frequency for the sweep and is added incrementally to the current output frequency. Note that the increment frequency can be positive or negative, thereby giving an increasing or decreasing frequency sweep. At the start of a sweep, the frequency contained in the FSTART register is output. Next, the frequency (FSTART + f ) is output. This is followed by (FSTART + f + f) and so on. Multiplying the f value by the number of increments (NINCR), and adding it to the start frequency (FSTART), gives the final frequency in the sweep. Mathematically this final frequency/stop frequency is represented by FSTART + (NINCR x f). The f register is a 23-bit register, and requires two 16-bit writes to be programmed. Table 9 gives the addresses associated with both the MSB and LSB registers of the f word. Table 9. f Register Bits
D15 0 0 0 D14 0 0 0 D13 1 1 1 D12 0 1 1 D11 D10 to D0 12 LSBs of f <11...0> 0 11 MSBs of f <22...12> 1 11 MSBs of f <22...12> Sweep Direction N/A Positive f (FSTART + f ) Negative f (FSTART - f )
Increment Interval (tINT)
The increment interval dictates the duration of the DAC output signal for each individual frequency of the frequency sweep. The AD5930 offers the user two choices: * * The duration is a multiple of cycles of the output frequency. The duration is a multiple of MCLK periods.
This is selected by Bit D13 in the tINT register as shown in Table 12. Table 12. tINT Register Bits
D15 0 D14 1 D13 0 D12 x D11 x D10 to D0 11 bits <10...0> Fixed number of output waveform cycles. 11 bits <10...0> Fixed number of clock periods.
0
1
1
x
x
Programming of this register is in binary form with the minimum number being decimal 2. Note in Table 12 that 11 bits, Bit D10 to Bit D0, of the register are available to program the time interval. As an example, if MCLK = 50 MHz, then each clock period/base interval is (1/50 MHz) = 20 ns. If each frequency needs to be output for 100 ns, then <00000000101> or decimal 5 needs to be programmed to this register. Note that the AD5930 can output each frequency for a maximum duration of 211 -1 (or 2047) times the increment interval.
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AD5930
Therefore, in this example, a time interval of 20 ns x 2047 = 40 s is the maximum, with the minimum being 40 ns. For some applications, this maximum time of 40 s may be insufficient. Therefore, to cater for sweeps that need a longer increment interval, time-base multipliers are provided. Bit D12 and Bit D11 are dedicated to the time-base multipliers (see Table 12). A more detailed table of the multiplier options is given in Table 13. Table 13. Time-Base Multiplier Values
D12 0 0 1 1 D11 0 1 0 1 Multiplier Value Multiply (1/MCLK) by 1 Multiply (1/MCLK) by 5 Multiply (1/MCLK) by 100 Multiply (1/MCLK) by 500
Table 14. TBURST Register Bits
D15 1 D14 0 D13 0 D12 x D11 x D10 to D0 11 bits of <0...10> Fixed number of output waveform cycles. 11 bits of <0...10> Fixed number of clock periods.
1
0
1
x
x
However, note that when using both the increment interval (tINT) and burst time register (TBURST), the settings for Bit D13 should be the same. In instances where they differ, the AD5930 defaults to the value programmed into the tINT register. Similarly, Bit 12 and Bit 11, the time-base multiplier bits, always default to the value programmed into the tINT register.
If MCLK is 50 MHz and a multiplier of 500 is used, then the base interval (TBASE) is now (1/(50 MHz) x 500)) = 10 s. Using a multiplier of 500, the maximum increment interval is 10 s x 211 - 1 = 20.5 ms. Therefore, the option of time-base multipliers gives the user enhanced flexibility when programming the length of the frequency window, because any frequency can be output for a minimum of 40 ns up to a maximum of 20.5 ms.
ACTIVATING AND CONTROLLING THE SWEEP
After the registers have been programmed, a 0 1 transition on the CTRL pin starts the sweep. The sweep always starts from the frequency programmed into the FSTART register. It changes by the value in the F register and increases by the number of steps in the NINCR register. However, both the time interval and burst duration of each frequency can be internally controlled using the tINT and TBURST registers, or externally using the CTRL pin. The options available are: 1. 2. 3. auto-increment, auto-burst control external increment, auto-burst control external increment, external burst control
Length of Sweep Time
The length of time to complete a user-programmed frequency sweep is given by the following equation: TSWEEP = (1 + NINCR) x TBASE
Burst Time Resister (TBURST)
As previously described in the Burst Output Mode section, the AD5930 offers the user the ability to output each frequency in the sweep for a length of time within the increment interval (tINT), and then return to midscale for the remainder of the time (tINT - TBURST) before stepping to the next frequency. The burst option must be enabled. This is done by setting Bit D7 in the control register to 0. Similar to the time interval register, the burst register can have its duration as: * * A multiple of cycles of the output frequency A multiple of MCLK periods
1. Auto-Increment, Auto-Burst Control
The values in the tINT and TBURST registers are used to control the sweep. The AD5930 bursts each frequency for the length of time programmed in the TBURST register, and outputs midscale for the remainder of the interval time (tINT - TBURST). To set up the AD5930 to this mode, CW/BURST (Bit D7) in the control register must be set to 0, INT/EXT BURST (Bit D6) must be set to 0, and INT/EXT INCR (Bit D5) must be set to 0. Note that if the part is only operating in continuous mode, then (Bit D7) in the control register should be set to 1.
The address for this register is given in Table 14.
2. External Increment, Auto-Burst Control
The time interval, tINT, is set by the pulse rate on the CTRL pin. The first 0 1 transition on the pin starts the sweep. Each subsequent 0 1 transition on the CTRL pin increments the output frequency by the value programmed into the F register. For each increment interval, the AD5930 outputs each frequency for the length of time programmed into the TBURST register, and outputs midscale until the CTRL pin is pulsed again. Note that for this mode, the values programmed into Bit D13, Bit D12, and bit D11 of the TBURST register are used.
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AD5930
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the control register must be set to 0, INT/EXT BURST (Bit D6) must be set to 0, and INT/EXT INCR (Bit D5) must be set to 1. Note that if the part is only operating in continuous mode, then Bit D7 in the control register should be set to 1.
OUTPUTS FROM THE AD5930
The AD5930 offers a variety of outputs from the chip. The analog outputs are available from the IOUT/IOUTB pins, and include a sine wave and a triangle output. The digital outputs are available from the MSBOUT pin and the SYNCOUT pin.
3. External Increment, External Burst Control:
Both the increment interval (tINT) and the burst interval (TBURST) are controlled by the CTRL pin. A 0 1 transition on the CTRL pin starts the sweep. The duration of CTRL high then dictates the length of time the AD5930 bursts that frequency. The low time of CTRL is the "listen" time, that is, how long the part remains at midscale. Bringing the CTRL pin high again initiates a frequency increment, and the pattern continues. For this mode, the settings for Bit D13, Bit D12, and Bit D11 are ignored. To setup the AD5930 to this mode, CW/BURST (Bit D7) in the control register must be set to 0, INT/EXT BURST (Bit D6) must be set to 1, and INT/EXT INCR (Bit D5) must be set to 1. Note that if the part is only operating in continuous mode, then Bit D7 in the control register should be set to 1.
Analog Outputs Sinusoidal Output
The SIN ROM is used to convert the phase information from the frequency register into amplitude information, which results in a sinusoidal signal at the output. To have a sinusoidal output from the IOUT/IOUTB pins, set Bit SINE/TRI (Bit D9) to 1.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC produces a 10-bit linear triangular function. To have a triangle output from the IOUT/IOUTB pins, set Bit SINE/TRI (D9) to 0. Note that the DAC ENABLE bit (D10) must be 1 (that is, the DAC is enabled) when using these pins.
VOUT MAX VOUT MIN p/2 5p/2 9p/2
05333-012
Interrupt Pin
This function is used as an interrupt during a frequency sweep. A low-to-high transition on this pin is sampled by the internal MCLK, thereby resetting internal state machines, which results in the output going to midscale.
3p/2
7p/2
11p/2
Figure 34. Triangle Output
Standby Pin
Sections of the AD5930 that are not in use can be powered down to minimize power consumption. This is done by using the STANDBY pin. For the optimum power savings, it is recommended to reset the AD5930 before entering standby, because doing so reduces the power-down current to 20 A. When this pin is high, the internal MCLK is disabled, and the reference, DAC, and regulator are powered down. When in this state, the DAC output of the AD5930 remains at its present value as the NCO is no longer accumulating. When the device is taken back out of standby mode, the MCLK is re-activated and the sweep continues. To ensure correct operation for new data, it is recommended that the device be internally reset using a control register write or using the INTERRUPT pin, and then restarted.
Digital Outputs Square Wave Output from MSBOUT
The inverse of the MSB from the NCO can be output from the AD5930. By setting the MSBOUTEN (D8) control bit to 1, the inverted MSB of the DAC data is available at the MSBOUT pin. This is useful as a digital clock source.
DVDD
05333-013
DGND
Figure 35. MSB Output
SYNCOUT Pin
The SYNCOUT pin can be used to give the status of the sweep. It is user selectable for the end of the sweep, or to output a 4 x TCLOCK pulse at frequency increments. The timing information for both of these modes is shown in Figure 6 and Figure 7. The SYNCOUT pin must be enabled before use. This is done using Bit D2 in the control register. The output available from this pin is then controlled by Bit D3 in the control register. See Table 5 for more information.
Rev. 0 | Page 21 of 28
AD5930 APPLICATIONS
GROUNDING AND LAYOUT
The printed circuit board that houses the AD5930 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD5930 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5930. If the AD5930 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD5930. Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD5930 to avoid noise coupling. The power supply lines to the AD5930 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD5930 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD5930, it is recommended that the system's AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD5930 and AGND, and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. Proper operation of the comparator requires good layout strategy. The strategy must minimize the parasitic capacitance between VIN and the SIGN BIT OUT pin by adding isolation using a ground plane. For example, in a multilayered board, the VIN signal could be connected to the top layer and the SIGN BIT OUT connected to the bottom layer, so that isolation is provided between the power and ground planes.
Interfacing to Microprocessors
The AD5930 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data/control information is being written to the AD5930, FSYNC is taken low and is held low while the 16 bits of data are being written into the AD5930. The FSYNC signal frames the 16 bits of information being loaded into the AD5930.
AD5930 TO ADSP-21xx INTERFACE
Figure 36 shows the serial interface between the AD5930 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT transmit alternate framing mode (TFSW = 1). The ADSP-21xx are programmed through the SPORT control register and should be configured as follows: 1. 2. 3. 4. 5. Internal clock operation (ISCLK = 1) Active low framing (INVTFS = 1) 16-bit word length (SLEN = 15) Internal frame sync signal (ITFS = 1) Generate a frame sync for each write (TFSR = 1)
Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD5930 on the SCLK falling edge.
ADSP-2101/ ADSP-21031
TFS DT SCLK
AD59301
FSYNC SDATA SCLK
05333-038
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 36. ADSP-2101/ADSP-2103 to AD5930 Interface
Rev. 0 | Page 22 of 28
AD5930
AD5930 TO 68HC11/68L11 INTERFACE
Figure 37 shows the serial interface between the AD5930 and the 68HC11/68L11 controller. The controller is configured as the master by setting bit MSTR in the SPCR to 1, which provides a serial clock on SCK while the MOSI output drives the serial data line SDATA. Since the controller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows: 1. 2. SCK idles high between write operations (CPOL = 0)
80C51/80L511
a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/80L51 outputs the serial data in an LSB first format. The AD5930 accepts the MSB first (the 4 MSBs being the control information, the next 4 bits being the address while the 8 LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first.
AD59301
Data is valid on the SCK falling edge (CPHA = 1)
P3.3 RXD TXD FSYNC SDATA SCLK
05333-040
When data is being transmitted to the AD5930, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data into the AD5930, PC7 is held low after the first 8 bits are transferred and a second serial write operation is performed to the AD5930. Only after the second 8 bits have been transferred should FSYNC be taken high again.
68HC11/68L111
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 38. 80C51/80L51 to AD5930 Interface
AD5930 TO DSP56002 INTERFACE
Figure 39 shows the interface between the AD5930 and the DSP56002. The DSP56002 is configured for normal mode, asynchronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on Pin SC2, but needs to be inverted before being applied to the AD5930. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002.
DSP560021
AD59301
PC7 MOSI SCK
FSYNC SDATA SCLK
05333-039
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 37. 68HC11/68L11 to AD5930 Interface
AD5930 TO 80C51/80L51 INTERFACE
Figure 38 shows the serial interface between the AD5930 and the 80C51/80L51 controller. The controller is operated in mode 0 so that TXD of the 80C51/80L51 drives SCLK of the AD5930, while RXD drives the serial data line SDATA. The FSYNC signal is again derived from a bit programmable pin on the port (P3.3 being used in the diagram). When data is to be transmitted to the AD5930, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus, only eight falling SCLK edges occur in each cycle. To load the remaining 8 bits to the AD5930, P3.3 is held low after the first 8 bits have been transmitted, and
AD59301
SC2 STD SCK
FSYNC SDATA SCLK
05333-041
1ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 39. DSP56002 to AD5930 Interface
Rev. 0 | Page 23 of 28
AD5930
EVALUATION BOARD
The AD5930 evaluation board allows designers to evaluate the high performance AD5930 DDS modulator with minimum effort. The evaluation board interfaces to the USB port of a PC. It is possible to power the entire board off the USB port. All that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. The DDS evaluation kit includes a populated and tested AD5930 printed circuit board. The EVAL-AD5930EB kit is shipped with a CD-ROM that includes self-installing software. The PC is connected to the evaluation board using the supplied cable. The software is compatible with Microsoft(R) Windows(R) 2000 and Windows XP. A schematic of the evaluation board is shown in Figure 40 and Figure 41.
Using the AD5930 Evaluation Board
The AD5930 evaluation kit is a test system designed to simplify the evaluation of the AD5930. An application note is also available with the evaluation board and gives full information on operating the evaluation board.
Prototyping Area
An area is available on the evaluation board for the user to add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application.
XO vs. External Clock
The AD5930 can operate with master clocks up to 50 MHz. A 50 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock can be connected to the part.
Rev. 0 | Page 24 of 28
SCHEMATIC
02 A K 3.3V 3.3V R17 0 R0603 C12 0.1F C0603 LED R3 1k R0603
1 GL2 2
GROUND LINK
ADP3303-3.3
1
+ + 3.3V C7 0.1F C0603 AVCC 3 VCC VCC VCC VCC VCC VCC VCC 7 11 17 27 32 43 55 R4 100k R0603 R17 100k R0603 C4 0.1F C0603 C3 0.1F C0603
C9 10F RTAJ_A
4
C8 0.1F C0603 U3 C5 0.1F C0603
8 7 5
IN1 IN2 SD 3.3V 3.3V
VCC 2 WP 6 SCL 3 NR GND
C10 2.2F RTAJ_A
3.3V C11 10F RTAJ_A + 3.3V 3.3V 24LC01
1 2 3 4
42 44 RESET *WAKEUP CLKOUT D- D+ U4 CY7C68013-CS P 54
J1
USB-MINI-B 9 8
AGND
3.3V
6
GND GND GND GND GND GND GND
T3 T6 T7
T4
T5
10 12 26 28 41 53 56
Figure 40. Page 1 of EVAL-AD5930EB Schematic
PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 CTL0/*FLAGA CTL1/*FLAGB CTL2/*FLAGC SDA SCL 1 2 13 14 RDY0/*SLRD RDY1/*SLWR IFCLK RSVD XTALOUT XTALIN 18 19 20 21 22 23 24 25 45 46 47 48 49 50 51 52 29 30 31 16 15 4 5 STANDBY INTERRUPT CTRL SDATA SCLK FSYNC 33 34 35 36 37 38 39 40 PA0/INT0 PA1/INT1 PA2/*SLOE PA3/*WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/*PKTEND PA7/*FLD/SLCS C33 0.1F C34 0.1F C35 0.1F C36 0.1F
Rev. 0 | Page 25 of 28
SHIELD
VBUS D- D+ IO GND
1 2 3 4 5
C6 22pF C0603 A0 A1 A2 VSS VCC 7 WP 6 SCL 5 SDA SDA SCL
8
R2 2.2k R0603
R1 2.2k R0603
3.3V
C28 0.1F
C30 0.1F
C32 0.1F
Y1 24MHz C1 22pF C0603 C2 22pF C0603
05333-023
AD5930
AD5930
T21 DVDD LK1 AB BEAD J14-1 AGND C29 10F RTAJ_A J14-2 C31 0.1F C0603 DVDD C14 0.1F C0603 C13 10F RTAJ_A AVDD 1 2 BA T23 T24 3.3V L1 LK8 J2-1 SDATA DGND J2-2 J5 R16 1.5k AVDD
T22
FSYNC J4
SCLK
J3
S1B 6 S2B 10 S3B 13 S4B
3
DVDD + C15 0.1F C0603 AVDD C19 10F RTAJ_A T26 FS_A C20 0.1F C0603 + DVDD
2 5 11 14 4 7 9 12
DVDD
16
VDD
C16 10F RTAJ_A
REF C22 0.1F C0603 IOUT
REF J15
C37 0.1F C0603
FSYNC SCLK SDATA
D1 S1A D2 S2A D3 S3A D4 S4A IN EN GND
1 8 15
IOUT C24 C0603 J11
LK2 DVDD C17 0.1F C0603 LK7
ADG774
AB
R7 200 R0603 C21 C0603 IOUTB
6
5
4
CTRL CTRL FSYNC SCLK SDATA 15 14 SCLK SDATA REF COMP U1 AD5930 IOUT IOUTB MSBOUT MCLK DGND O/P SYNCOUT DGND AGND CTRL INTERRUPT STANDBY 2 3 16 FSYNC FSADJUST 1 CAP/2.5V DVDD AVDD CTRL
LK4
R6 6.8k R0603 C23 0.01F C0603 AVDD
IOUTB C25 C0603 MSBOUT J12
11
7
AB R12 10k R0603 T25 MCLK DVDD C17 0.1F C0603
8
18
Figure 41. Page 2 of EVAL-AD5930EB Schematic
INT INTERRUPT 13 12 17 8 19 20 10 9 STANDBY STANDBY SURFACE MOUNT AREA THROUGH HOLE AREA GL1 GROUND LINK O/P
14
Rev. 0 | Page 26 of 28
R15 R0603 VDD U7 50MHZ_XTAL 7 GND
J6
AB R10 10k R0603
R8 200 R0603
MSBOUT C26 C0603 SYNCOUT J10
INTERRUPT
LK5
J7
AB R11 10k R0603
SYNCOUT C18 C0603 J9
STANDBY
LK6
J8
MCLK
LK6
J13
AB R9 49.9k R0603
05333-024
AD5930 OUTLINE DIMENSIONS
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 42. 20-Lead Thin Shrink Small Outline Package (TSSOP) (RU-20) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5930YRUZ1 AD5930YRUZ-REEL71 EVAL-AD5930EB
1
Temperature Range -40C to +105C -40C to +105C
Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board
Package Option RU-20 RU-20
Z = Pb-free part.
Rev. 0 | Page 27 of 28
AD5930 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05333-0-11/05(0)
Rev. 0 | Page 28 of 28

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